1. Field of the Invention
This invention relates to a data processing system in which a program being executed can access operands in a plurality of spaces concurrently, and more particularly to a data processing system for performing access register (AR) translation when obtaining a base address (STO) (Segment Table Origin) of a translation table to be used for translation from a logical address into a real address.
2. Description of the Related Art
According to the ESA/370 (Enterprise System Architecture/370) architecture of IBM (International Business Machines) Corporation, in order to select one address space from multiple virtual address spaces, it is possible to designate a space identifier (hereinafter also called ALET (Access List Entry Token)) by an access register (hereinafter also called AR) corresponding to a base register to be used in computing an operand logical address of an instruction and also possible to obtain a base address (hereinafter also called STO) of a translation table, which is prepared in the virtual address space by a table indexing means (i.e., access register translation; hereinafter also called AR translation or ART) which is provided by the system to the ALET. This architecture also includes a memory (hereinafter called ALB (ART Look-aside Buffer) for storing translation pairs of the ALET and STO, thereby reducing the amount of time taken for the AR translation.
In the meantime,
1) The STO to be obtained is a primary STO (hereinafter called PSTO) retained in a control register No. 1 when the ALET retained in the AR corresponding to a designated base register number is `0`. PA1 2) The STO to be obtained is a secondary STO (hereinafter called SSTO) retained in a control register No. 7 when the ALET is `1`. PA1 (1) whether or not the ALET is `0`, and PA1 (2) whether or not the ALET is `1`.
This prior art system is exemplified by Japanese Patent Publication No. 60-41379(B2).
With any of the foregoing prior art systems, in the process (i.e. AR translation) for obtaining the STO from the ALET retained in the AR corresponding to the base register number, which process occurs at a time between the operand address computing and the operand data read for an instruction, the following two discriminating processes would be necessary:
When the ALET is neither `0` nor `1` in these two discriminating processes (1) and (2), the STO is obtained referring to the ALB in which translation pairs of ALET and STO are stored. In addition, when there is no translation pair to be obtained in the ALB, the STO is obtained by AR translation.
Consequently, overhead due to these two discriminating processes (1) and (2) would be caused by the time STO is obtained.